1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and more specifically, to a method for fabricating a crown-type capacitor of a dynamic random access memory (DRAM) cell, thereby improving the uniformity of a spacer in the capacitor structure, and providing a larger process window.
2. Description of Related Art
A conventional DRAM cell, referring to FIG. 1, consists of a transistor T and a capacitor C. The source of the transistor T is connected to a corresponding bit line BL. The drain of the transistor T is connected to a storage electrode of the capacitor C. The gate of the transistor is connected to a corresponding word line WL. An opposite electrode of the capacitor C is biased with a constant voltage source. A dielectric layer is arranged between the storage electrode and the opposite electrode. As known to those skilled in the art, the storage capacitor C is provided for data storage. Therefore, a large capacitance is required for the capacitor to prevent data loss and to lower the refresh rate.
For a conventional DRAM of less than 1 MB capacity, a two-dimensional capacitor structure is utilized for data storage. This capacitor structure is well known as a planar-type capacitor. However, in order to provide a capacitance large enough for data storage, the planar-type capacitor occupies a very large base area. This structure cannot therefore be applied in a high-density DRAM process.
Accordingly, some three-dimensional capacitor structures, such as a trench-type or stack-type structure, have been developed to satisfy the requirement of a high-integrated DRAM device of more than 16 MB. However, the trench-type structure has, evidently, defects in the substrate during the trench formation, thereby increasing leakage current and affecting the device performance. Moreover, since the etching rate of the trench decreases as the aspect ratio increases, the process becomes more difficult, and the DRAM productivity is reduced. Therefore, the trench-type structure is not that applicable in reality. The stack-type capacitor, on the contrary, is free of all the problems mentioned above. It is therefore very popular in small-dimensional memory fabrication, and has attracted a lot of attention regarding structure optimization.
Among all kinds of stack-type capacitors, a crown-type capacitor in which an electrode has an upward extending portion to provide a very large area for data storage is favorable for highly-integrated memory devices, especially for those have a capacity of more than 64 MB. The upward extending electrode can be fabricated by, for example, anisotropically etching a conducting polysilicon layer through a spacer mask. This electrode is a storage electrode. As a crown-type capacitor of a DRAM cell, the capacitor further includes a dielectric layer over the storage electrode, and an opposite electrode over the dielectric layer.
However, the steps to fabricate a crown-type capacitor are numerous and complicated, thereby affecting the DRAM productivity. Even though some process modification has simplified the steps, the process conditions have become correspondingly stricter, and are not applicable in DRAM production.
The conventional process steps of a crown-type capacitor for a DRAM cell will be described in accompaniment with the drawings of FIG. 2A through FIG. 2C. Referring to FIG. 2A, a field oxide layer 12 is formed over a semiconductor substrate 10, which is, for example, a silicon substrate, to define an active region thereon. Then a gate oxide layer 13, a polysilicon layer 14, a tungsten silicide (WSi.sub.x) 15, and an insulating layer 16 are successively formed over the active region, and are etched to be a gate electrode G. By using the gate electrode G as a mask, impurities are implanted into the semiconductor substrate 10 to form lightly-doped source/drain regions 17a and 17b. A spacer 18 is formed on the sidewall on the gate structure G by depositing a dielectric layer and etching back the dielectric layer. Then the gate structure G and the spacer 18 are both utilized as a mask for further implanting impurities into the semiconductor substrate 10 to form heavily-doped source/drain regions 19a and 19b, thereby forming a transistor.
The transistor is successively covered by a first planar layer 20 and a second planar layer 21 which are both etched to form a contact window (not shown in the figure), by micro-lithography and etching, to expose the drain region 19b of the transistor. Then a first conducting layer is formed over the first planar layer 20 to fill the contact window, thereby electrically connecting the drain region 19b. This conducting layer is patterned to be a bit line of the memory device. Then a BPSG layer 22 is deposited over the first planar layer 20 and the exposed bit line surface. A contact opening is then formed through the first planar layer 20, the second planar layer 21 and the BPSG layer 22 by microlithography and etching, to expose the source region 19a as a contact region. A conducting layer 24, such as a doped polysilicon layer, is deposited over the BPSG layer 22 and fills in the contact opening 23, thereby electrically contacting the contact region.
The micro-lithography and etching steps are successively carried out to form several shallow trenches on the conducting layer 24, thereby separating several memory cell regions, that is, regions between the contact openings 23. Then a dielectric layer is deposited and etched back to form dielectric spacers 30 on the sidewalls of the shallow trenches 26.
The critical step for forming the crown-type capacitor will be described in accompaniment with the schematic diagram of FIG. 2B. Referring to FIG. 2B, using the dielectric spacers 30 as a mask, the conducting layer 24 is anisotropically etched by, for example, the reactive ion etching (RIE) method to remove the portions under the shallow trenches 26, thereby defining the capacitor regions. Since the remaining conducting layer 24 has a constant thickness of t1, a storage electrode 24 having the crown-type structure 24a is formed.
Referring to FIG. 2C, the dielectric spacers 30 are then removed. The storage electrode 24 is successively covered by a dielectric layer 27 and an opposite electrode 28, thereby forming a capacitor. The complete DRAM cell further includes a passivation layer 29 over the capacitor.
The aforementioned fabrication method utilizes the dielectric spacer 30 as a mask for anisotropically etching the conducting layer, thereby forming the crown-type structure and defining the capacitor region. Therefore, the etching condition must be precisely controlled. In order to isolate each capacitor, over etching the conducting layer is generally required, therefore reducing the conductivity due to an insufficient thickness of t1. Moreover, the crown-type structure may be broken, thereby affecting the performance of the device. Furthermore, since the crown-type structure is defined by the spacers 30, the shape of the spacers 30 transfers to the electrode structure, and a sharp-point discharge will happen to the device.